Key Dates

Submission Deadline

June 2, 2015

Author Notification

June 30, 2015

Paper for Workshop

July 31, 2015


August 25, 2015

Paper Camera Ready

October 2, 2015


Submit your paper here
(track UCHPC)

Hosting Conference

Previous Workshops

2014 @ EuroPar'14
2013 @ EuroPar'13
2012 @ EuroPar'12
2011 @ EuroPar'11
2010 @ EuroPar'10
2009 @ CF'09
2008 @ ICCSA'08


The workshop takes place on Tuesday, August 25 in Room "EI 2" (Pichelmayer HS) of the building "Gußhausstraße 25" (1040 Wien), see site map. Registration is at the Euro-Par conference venue at Gußhausstraße 27-29.

14:00 Workshop opening
by Josef Weidendorfer, Jens Breitbart
14:10 - 16:00 Session 1
Chair: Jens Breitbart
14:10 Keynote (abstract)
The Active Memory Cube: A Processing-in-Memory System for High Performance Computing
by Zehra Sura, IBM (Slides)
15:00 Energy-performance tradeoffs for HPC applications on low power processors
by Enrico Calore, Sebastiano Fabio Schifano, Raffaele Tripiccione (Slides)
15:30 Optimized Force Calculation of Molecular Dynamics Simulations for the Intel Xeon Phi
by Nikola Tchipev, Amer Wafai, Colin W. Glass, Wolfgang Eckhardt, Alexander Heinecke, Hans-Joachim Bungartz, Philipp Neumann (Slides)
16:00 (coffee break)
16:30 - 17:30 Session 2
Chair: Peter Zinterhof
16:30 Towards Application Variability Handling with Component Models: 3D-FFT Use Case Study
by Richard Jérôme, Lanore Vincent, Perez Christian
17:00 A cache-aware performance prediction framework for GPGPU computations
by Alexander Pöppl, Alexander Herz (Slides)
17:30 Best Paper Award Ceremony and Workshop Closing
by Josef Weidendorfer, Jens Breitbart

Best Paper Award

This years best paper award goes to the paper "Energy-performance tradeoffs for HPC applications on low power processors" by Enrico Calore, Sebastiano Fabio Schifano, Raffaele Tripiccione.


As in recent years, we had a price to give out. This year it was a ARM 64-bit development board (8-core Cortex-A53) we got sponsored from ARM university (the "HiKey" built by 96Boards). The board is supported by Linaro with ready-to-run image files, and it is great both for research (you can measure power consumption at two points) and education (also in our own interest).


The Active Memory Cube:
A Processing-in-Memory System for High Performance Computing

Abstract: Next-generation high performance computing systems need to be more power-performance efficient, but the increasing cost of data movement is a major bottleneck in developing these systems. The Active Memory Cube (AMC) project at IBM T.J. Watson addressed this challenge, leveraging 3D stacked memory to move processing closer to data. This talk will describe our experience with the AMC system, the architecture design and tradeoffs made for power-efficiency, and the ramifications on system software, compilers, and programming API.

Dr. Zehra Sura is a Research Scientist at the IBM T.J. Watson Center in Yorktown Heights, New York. She is interested in compilers and architecture, with special interest in parallel computing, multithreading, and memory access optimization. She has worked on several high performance computing architectures, including systems with GPUs, the Active Memory Cube, the BlueGene/Q system, and the Cell Broadband Engine. Prior to joining IBM in 2004, she completed her PhD in Computer Science from the University of Illinois at Urbana-Champaign.